Generally, a test pattern used in a semiconductor test system for testing a semiconductor device is very lengthy and large scale. Further, in a semiconductor memory testing, for example, a test pattern tends to repeat the same portion of test pattern many times. Furthermore, generating such test a pattern with high speed is required because of the increase of the speed in the recent semiconductor devices to be tested.
A test pattern generator currently in use is basically formed of an accumulator type arithmetic unit which generates a long and large scale test pattern by programming arithmetic instructions and numbers of repetition in a program memory of the test pattern generator.
FIG. 10 shows an example of a conventional arithmetic circuit for the test pattern generator. The arithmetic circuit includes a control circuit 3, an arithmetic unit 1 and a register 2. The control circuit 3 has a program memory 31 and a clock generator 32 therein. A command read out from the program memory is provided to an input terminal A of the arithmetic unit 1. The output of the arithmetic unit 1 is connected to the register 2 whose output is connected to an input terminal B of the arithmetic unit 1. Also, an operation clock from the clock generator 32 is applied to a clock input terminal of the register 2. The resulted output X is obtained from the output of the arithmetic unit 1.
FIG. 11 shows an example of operation that implements a program example 1 with the use of the arithmetic circuit of FIG. 10.
First, an initial value "X=0" is stored in the first line of the program memory 31. In the next line, the instruction "Repeat 11 X=X+1" is stored which means to repeat an addition of one (1) for 11 times. In the third line of the program memory 31, in order that output value X be unchanged (remained as X), "X=X" is described. Thus, as in the foregoing, instruction data for the arithmetic unit 1 consists of a set of a numerical value, a sign and a command.
Therefore, at a first operation cycle, X=0 command is given to the terminal A of the arithmetic unit 1 from the program memory 31. The arithmetic unit 1 performs arithmetic operation. In the arithmetic unit 1, since the command from the memory 31 is X=0, the arithmetic unit 1 receives "0" as its input value without regard to the input value of other input terminal B. Thus, the value "0" is obtained as an output X of the arithmetic unit 1.
Next, the operation clock is applied to the register 2. In response to the clock, the register 2 latches 0 and its output value becomes 0. This numerical value is applied to another input terminal B of the arithmetic unit 1. Since the input terminal A is given X=+1 in this cycle and the input terminal B is given the value 0, the arithmetic operation "0+1" is performed by the arithmetic unit 1. The arithmetic unit 1 obtains an output X=1 as the result. Like this, only a numerical value and a sign are applied to another input terminal B of the arithmetic unit 1.
In the third operation cycle, "+1" command is continuously given at the terminal A, the arithmetic operation of plus one is carried out for the previous output value X=1 (terminal B). Therefore, an output X=2 is obtained as the result at the output of the arithmetic unit 1. In this manner, the arithmetic operation of the "+1" addition is carried out 11 (eleven) times.
In the above operational procedure in the conventional test pattern generator, the output of the register 2 changes its state by receiving the operation clock and the arithmetic unit 1 performs an arithmetic operation on the basis of the output value of the register 2. After the time required for this operation, supply of the operation clock for the next cycle becomes possible. This operation clock cycle composes the shortest pass of the pattern generation procedure. Accordingly, the time interval of the clock is the highest computation speed in this conventional test pattern generator.
FIG. 12 shows another example of arithmetic circuit in the conventional test pattern generator. In this example, the method of increasing the test pattern generating speed is accomplished by simply including a plurality of arithmetic units in a parallel form. Yet instructions for each arithmetic unit have to be prepared beforehand to accomplish this parallel operation.
In the example of FIG. 12, four arithmetic units 11.varies.14, four registers 21-24 and four program memories 41-44 are provided in parallel. Each set of the arithmetic unit, the register and the program memory is identical to the structure of FIG. 10. The registers 21-24 commonly receives a clock signal from a clock generator 45. The outputs X.sub.0, X.sub.1, X.sub.2 and X.sub.3 of the arithmetic units 11-14 are provided to a multiplexing circuit 5 which is also provided with a clock from the clock generator 45. The clock rate for the multiplexing circuit in this example should be four times faster than the example of FIG. 10 since the four arithmetic units 11-14 are provided in parallel.
Art example of configuration of the multiplexing circuit 5 is shown in FIG. 6. As shown in FIG. 6, the multiplexing circuit includes a multiplexer 502 and a counter 501. The counter 501 receives the clock from the clock generator 45 and outputs a 2-bits signal for the multiplexer 502. The 2-bits signal works as a select signal for the multiplexer 502. The outputs X.sub.0, X.sub.1, X.sub.2 and X.sub.3 of the arithmetic units 11-14 are multiplexed by the multiplexer 502 by the timing of the select signal from the counter 501 and the selected one of outputs is provided at the output terminal of the multiplexing circuit 5 as a resulted output X having four times faster speed than the data from the arithmetic units 11-14.
FIG. 7 is a timing chart showing a basic operation of the multiplexing circuit of FIG. 6. As is well known in the art, n parallel data provided to a multiplexer can be converted to a serial data having an n-times faster speed than that in each of the parallel data. In FIG. 7, input signals X.sub.0, X.sub.1, X.sub.2 and X.sub.3 having data a, b, c and d, respectively, supplied in parallel to the multiplexer 502 are converted to an output signal X having the data a, b, c and d in series which is four times faster than each of the input signals.
FIG. 13 is a schematic view showing an example of operation of the arithmetic circuit of FIG. 12 for implementing a test pattern generation based on a program example 1. As shown in a table of FIG. 13A, the program example 1 includes an initial value stored in the program memory 41, which is provided to the arithmetic unit 11. The initial value for the arithmetic unit 11 is: EQU X.sub.0 =0.
The initial value for the arithmetic unit 12 stored in the program memory 42 is: EQU X.sub.1 =1.
The initial value for the arithmetic unit 13 stored in the program memory 43 is: EQU X.sub.2 =2.
The initial value for the arithmetic unit 14 store in the program memory 44 is: EQU X.sub.3 =3.
These initial values are provided to corresponding input terminals of the arithmetic units 11-14 in the first cycle as shown in FIG. 13B. Accordingly, output data of the arithmetic units 11-14 in the first cycle represent the same value 0, 1, 2 and 3 as shown in FIG. 13B.
The next value for the arithmetic unit 11 and stored the program memory 41 is: EQU Repeat 2 X.sub.0 =X.sub.0 +4.
The next value for the arithmetic unit 12 and stored the program memory 42 is: EQU Repeat 2 X.sub.1 =X.sub.1 +4.
The next value for the arithmetic unit 13 and stored the program memory 43 is: EQU Repeat 2 X.sub.2 =X.sub.2 +4.
The next value for the arithmetic unit 14 and stored in the program memory 44 is: EQU X.sub.3 =X.sub.3 +4.
Accordingly, in the second cycle, each of the arithmetic units 11-14 adds four (4) to the data of the first cycle, since each of the registers 21-24 returns the previous data to other input terminals of the arithmetic units as shown in FIG. 13C. As a result, in the second cycle, the output data of the arithmetic units 11-13 represent 4, 5, 6 and 7 as shown in FIG. 13C.
In the third cycle, since the instruction for the arithmetic unit 11 is the same as the previous cycle, i.e., "Repeat 2 X.sub.0 =X.sub.0 +4" which requires to repeat the addition of four (4), the output data of the arithmetic unit 11 becomes 8 as shown in FIG. 13D. Similarly, in the third cycle, since the instructions for the arithmetic units 12 and 13 are also the same as that of the previous cycle, i.e., "Repeat 2 X.sub.1 =X.sub.1 +4" and "Repeat 2 X.sub.2 =X.sub.2 +4", respectively, the output data of the arithmetic units 12 and 13 become 9 and 10, respectively, as shown in FIG. 13D.
The output data of the arithmetic unit 14 in the third cycle represents 10 because of the instruction in the program memory 44 indicates: EQU X.sub.3 =X.sub.3 +3.
As described above, compared with the conventional example of FIGS. 10 and 11, the test pattern generation speed increases by the number of arithmetic units provided in parallel (4 times in the example of FIG. 12). However, since the program to be stored in the program memories 41-44 becomes complicated as exemplified above, and thus, a program development procedure for this example is time consuming and tedious.